Low Power VLSI Design : Fundamentals

Name: Low Power VLSI Design : Fundamentals
Author: Angsuman Sarkar, Swapnadip De, Manash Chanda, Chandan Kumar Sarkar
ISBN: 9783110455267

by Angsuman Sarkar, Swapnadip De, Manash Chanda, Chandan Kumar Sarkar

Hardcover

Low Power VLSI Design : Fundamentals

by Angsuman Sarkar, Swapnadip De, Manash Chanda, Chandan Kumar Sarkar

Hardcover

Overview

This book teaches basic and advanced concepts, new methodologies and recent developments in VLSI technology with a focus on low power design. It provides insight on how to use Tanner Spice, Cadence tools, Xilinx tools, VHDL programming and Synopsis to design simple and complex circuits using latest state-of-the art technologies. Emphasis is placed on fundamental transistor circuit-level design concepts.

FormatHardcover

LanguageEnglish

Publisherde Gruyter GmbH, Walter

Publication DateAug. 8th, 2016

GradeHigher Education

ISBN-139783110455267

ISBN-103110455269

Shipping Weight1.50 lbs

All Available Copies Find out more about shipping times from these sellers.

Condition	Price
New (195 available) Brand new; direct from the publisher or distributor. Ships Separately	{{localize.CurrencySymbol}}279.22 {{localize.CurrencyAbbrev}}	Add To {{CartName}}	Ships separately from Better World Books suppliers
eBook Obtain a digital book from our friends at eBooks.com. eBooks.com	{{ebooksDotComPrice}} {{ebooksDotComCurrency}}	eBooks.com	Digital edition from eBooks.com
Audio Book Obtain a digital book from our friends at AudiobooksNow.com. AudiobooksNow.com	{{audioBooksNowPrice}} {{audioBooksNowCurrency}}	AudiobooksNow.com	Digital edition from AudiobooksNow.com

Introduction to Low Power Issues in VLSI	p. 1
Introduction to VLSI	p. 1
Low Power IC Design beyond Sub-20 nm Technology	p. 2
Issues Related to Silicon Manufacturability and Variation	p. 3
Issues Related to Design Productivity	p. 4
Limitation Faced by CMOS	p. 4
International Technology Roadmap for Semiconductors	p. 5
Different Groups of MOSFETs	p. 8
Three MOS Types	p. 9
Low Leakage MOSFET	p. 9
Importance of Subthreshold Slope	p. 10
Why Is Subthreshold Current Exponential in Nature?	p. 13
Subthreshold Leakage and Voltage Limits	p. 15
Importance of Subthreshold Slope in Low Power Operation	p. 16
Ultralow Voltage Operation	p. 16
Low Power Analog Circuit Design	p. 17
Fundamental Consequence of Lowering Supply Voltage	p. 18
Analog MOS Transistor Performance Parameters	p. 19
Summary	p. 21
References	p. 22
Scaling and Short Channel Effects in MOSFET	p. 24
MOSFET Scaling	p. 24
International Technology Roadmap for Semiconductors	p. 24
Gate Oxide Scaling	p. 25
Gate Leakage Current	p. 25
Mobility	p. 26
High-k Gate Dielectrics	p. 26
Key Guidelines for Selecting an Alternative Gate Dielectric	p. 26
Materials	p. 26
Gate Tunneling Current	p. 27
Gate Length Scaling	p. 27
Introduction to Short Channel Effect in MOSFET	p. 27
Reduction of Effective Threshold Voltage	p. 28
Drain-induced Barrier Lowering	p. 28
Mobility Degradation and Surface Scattering	p. 30
Surface Scattering	p. 32
Hot Carrier Effect	p. 32
Punch-through Effect	p. 32
Velocity Saturation Effect	p. 32
Increase in Off-state Leakage Current	p. 34
Motivation for Present Research	p. 34
Lightly Doped Drain Structure	p. 35
Channel Engineering Technique	p. 36
Gate Engineering Technique	p. 37
Single Halo Dual Material Gate MOSFET	p. 37
Double Halo Dual Material Gate MOSFET	p. 38
Double Gate MOSFET	p. 38
Dual Material Double Gate MOSFET	p. 40
Triple Material Double Gate MOSFET	p. 41
FinFET	p. 41
Triple Gate MOSFET	p. 43
Gate-all-around MOSFET	p. 43
Surrounding Gate MOSFET	p. 43
Silicon Nanowires	p. 44
Fringing-induced Barrier Lowering	p. 45
Silicon-on-insulator MOSFETs	p. 45
Nonconventional Double Gate MOSFETs	p. 46
Tunnel Field-effect Transistor	p. 63
IMOS Device	p. 65
Summary	p. 65
References	p. 66
Advanced Energy-reduced CMOS Inverter Design	p. 71
Introduction	p. 71
Transfer Characteristics of Inverter	p. 71
Static CMOS Inverter in Super-threshold Regime	p. 73
Introduction to Sub-threshold Logic	p. 94
Summary	p. 107
References	p. 108
Advanced Combinational Circuit Design	p. 112
Introduction	p. 112
Static CMOS Logic Gate Design	p. 112
Complementary Properties of CMOS Logic	p. 112
CMOS NAND Gate	p. 113
CMOS NOR Gate	p. 113
Some More Examples of CMOS Logic	p. 115
XOR or Nonequivalence Gate Using CMOS Logic	p. 116
XOR-XNOR or Equivalence Gate Using CMOS Logic	p. 116
And-Or-Invert and Or-And-Invert Gates	p. 117
Full Adder Circuits Using CMOS Logic	p. 118
Pseudo-nMOS Gates	p. 120
Why the Name Is Pseudo-nMOS?	p. 123
Ratioed Logic	p. 123
Operation of Pseudo-nMOS Inverter	p. 124
Pass-transistor Logic	p. 125
Complementary Pass Transistor Logic	p. 127
Signal Restoring Pass Transistor Logic Design	p. 128
Sizing of Transistor in CMOS Design Style	p. 129
Introduction to Logical Effort	p. 132
Definitions of Logical Effort	p. 132
Delay Estimation by Logical Effort	p. 135
Introduction to Transmission Gate	p. 136
Use of CMOS TG as Switch	p. 138
2:1 Multiplexer Using TG	p. 141
XOR Gate Using TG -141
XNOR Gate Using TG	p. 143
Transmission Gate Adders	p. 144
More Examples of TG Logic	p. 144
Tristate Buffer	p. 145
Transmission Gates and Tristates	p. 146
Implementation of Combinational Circuit Using DTMOS Logic for Ultra low Power Application	p. 149
ECLR Structure	p. 154
Power Consumption	p. 175
Propagation Delay	p. 175
References	p. 175
Advanced Energy-reduced Sequential Circuit Design	p. 177
Introduction to Sequential Circuit	p. 177
Basics of Regenerative Circuits	p. 177
Basic SR Flip-Hop/Latch	p. 181
NAND Gate-based Negative Logic SR Latch	p. 183
Clocked SR Latch	p. 183
Clocked JK Latch	p. 185
Toggle Switch	p. 186
Master-slave Flip-flop	p. 186
D Latch	p. 187
Positive and Negative Latch	p. 188
Multiplexer-based Latch	p. 188
Master-slave Edge-triggered Flip-flops	p. 190
Timing Parameters for Sequential Circuits	p. 192
Timing of Multiplexer-based Master-slave Flip- flop	p. 194
The Sizing Requirements for the Transmission Gates	p. 195
Clock Skews due to Nonideal Clock Signal	p. 196
Design and Analysis of the Flip-flops Using DTMOS Style	p. 197
SR Latch and Flip-flop	p. 197
JK Latch and JK Flip-flop	p. 201
D Flip-flop	p. 202
Adiabatic Flip-flop	p. 205
References	p. 207
Introduction to Memory Design	p. 208
Introduction	p. 208
Types of Semiconductor Memory	p. 208
Memory Organization	p. 210
Introduction to DRAM	p. 212
One-transistor DRAM Cell	p. 213
Write	p. 214
Hold	p. 214
Read	p. 215
Capacitor in DRAM	p. 217
Refresh Operation of DRAM	p. 219
DRAM Types	p. 220
FPM DRAMS	p. 220
Extended Data Out DRAMs	p. 221
Burst EDO DRAMs	p. 221
ARAM	p. 221
Cache DRAM	p. 221
Enhanced DRAM (EDRAM)	p. 221
Synchronous DRAM	p. 222
Double Data Read DRAMs	p. 222
Synchronous Graphic RAM	p. 222
Enhanced Synchronous DRAMs	p. 222
Video DRAMs	p. 223
Window DRAMs	p. 223
Pseudo-static RAMs	p. 223
Rambus DRAMs	p. 223
Multibank DRAM	p. 224
Ferroelectric DRAM	p. 224
SOI DRAM	p. 225
Operating Principle	p. 225
Design Considerations of SOI DRAM	p. 226
Introduction to SRAM	p. 226
SRAM Cell and Its Operation	p. 227
SRAM Cell Failures	p. 228
Performance Metrics of SRAM	p. 228
Static Noise Margin	p. 228
Reliability Issues of 6-T SRAM	p. 229
Read-only Memory	p. 230
EPROM	p. 233
Electrically Erasable Programmable Read-only Memory (E²PROM)	p. 234
Flash Memory	p. 236
Summary	p. 238
References	p. 239
Analog Low Power VLSI Circuit Design	p. 242
Analog Low Power Design: Problems with Transistor Mismatch	p. 242
Mixed-signal Design with Sub-100 nm Technology	p. 243
Challenges in MS Design in Sub-100 nm Space	p. 244
Lack of Convergence of Technology	p. 244
Digital Scaling	p. 245
Memory Scaling	p. 246
Analog Scaling	p. 247
Degraded SNR	p. 247
Degradation in Intrinsic Gain	p. 248
Device Leakage	p. 248
Mismatch due to Reduced Matching	p. 248
Availability of Models	p. 248
Passives	p. 248
RF Scaling	p. 249
Issues Related with Power Devices	p. 250
Basics of Switched-capacitor Circuits	p. 250
Resistor Emulation Using SC Network	p. 251
Integrator Using SC Circuits	p. 252
SC Integrator Sensitive to Parasitic	p. 255
Low Power Switched-capacitor Circuit	p. 256
Current Source/Sink	p. 258
Technique to Increase Output Resistance	p. 261
Low Power Current Mirror	p. 263
Use of Current Mirrors in IC	p. 263
Simple Current Mirror	p. 265
Wilson Current Mirror	p. 267
Cascode Current Mirror	p. 268
Low Voltage Current Mirror	p. 270
Fundamentals of Current/Voltage Reference	p. 273
Another Way to Obtain Simple Bootstrap Voltage Reference Circuit with Start-up Circuit	p. 279
Bandgap Voltage Reference	p. 282
Positive TC Voltage	p. 282
Negative TC Voltage	p. 283
An Introduction to Analog Design Automation	p. 284
Survey of Previous Analog Design Flow	p. 285
Analog and Mixed-signal Design Process	p. 288
Hierarchical Analog Design Methodology	p. 290
Current Status for the Main Tasks in Analog Design Automation	p. 292
Field-programmable Analog Arrays	p. 299
Summary	p. 301
References	p. 301
Index	p. 305
Table of Contents provided by Ingram. All Rights Reserved.

Find at your local library from our friends at WorldCat	Find Libraries

Overview

Product Details

FormatHardcover

LanguageEnglish

Publisherde Gruyter GmbH, Walter

Publication DateAug. 8th, 2016

GradeHigher Education

ISBN-139783110455267

ISBN-103110455269

Shipping Weight1.50 lbs

Introduction to Low Power Issues in VLSI	p. 1
Introduction to VLSI	p. 1
Low Power IC Design beyond Sub-20 nm Technology	p. 2
Issues Related to Silicon Manufacturability and Variation	p. 3
Issues Related to Design Productivity	p. 4
Limitation Faced by CMOS	p. 4
International Technology Roadmap for Semiconductors	p. 5
Different Groups of MOSFETs	p. 8
Three MOS Types	p. 9
Low Leakage MOSFET	p. 9
Importance of Subthreshold Slope	p. 10
Why Is Subthreshold Current Exponential in Nature?	p. 13
Subthreshold Leakage and Voltage Limits	p. 15
Importance of Subthreshold Slope in Low Power Operation	p. 16
Ultralow Voltage Operation	p. 16
Low Power Analog Circuit Design	p. 17
Fundamental Consequence of Lowering Supply Voltage	p. 18
Analog MOS Transistor Performance Parameters	p. 19
Summary	p. 21
References	p. 22
Scaling and Short Channel Effects in MOSFET	p. 24
MOSFET Scaling	p. 24
International Technology Roadmap for Semiconductors	p. 24
Gate Oxide Scaling	p. 25
Gate Leakage Current	p. 25
Mobility	p. 26
High-k Gate Dielectrics	p. 26
Key Guidelines for Selecting an Alternative Gate Dielectric	p. 26
Materials	p. 26
Gate Tunneling Current	p. 27
Gate Length Scaling	p. 27
Introduction to Short Channel Effect in MOSFET	p. 27
Reduction of Effective Threshold Voltage	p. 28
Drain-induced Barrier Lowering	p. 28
Mobility Degradation and Surface Scattering	p. 30
Surface Scattering	p. 32
Hot Carrier Effect	p. 32
Punch-through Effect	p. 32
Velocity Saturation Effect	p. 32
Increase in Off-state Leakage Current	p. 34
Motivation for Present Research	p. 34
Lightly Doped Drain Structure	p. 35
Channel Engineering Technique	p. 36
Gate Engineering Technique	p. 37
Single Halo Dual Material Gate MOSFET	p. 37
Double Halo Dual Material Gate MOSFET	p. 38
Double Gate MOSFET	p. 38
Dual Material Double Gate MOSFET	p. 40
Triple Material Double Gate MOSFET	p. 41
FinFET	p. 41
Triple Gate MOSFET	p. 43
Gate-all-around MOSFET	p. 43
Surrounding Gate MOSFET	p. 43
Silicon Nanowires	p. 44
Fringing-induced Barrier Lowering	p. 45
Silicon-on-insulator MOSFETs	p. 45
Nonconventional Double Gate MOSFETs	p. 46
Tunnel Field-effect Transistor	p. 63
IMOS Device	p. 65
Summary	p. 65
References	p. 66
Advanced Energy-reduced CMOS Inverter Design	p. 71
Introduction	p. 71
Transfer Characteristics of Inverter	p. 71
Static CMOS Inverter in Super-threshold Regime	p. 73
Introduction to Sub-threshold Logic	p. 94
Summary	p. 107
References	p. 108
Advanced Combinational Circuit Design	p. 112
Introduction	p. 112
Static CMOS Logic Gate Design	p. 112
Complementary Properties of CMOS Logic	p. 112
CMOS NAND Gate	p. 113
CMOS NOR Gate	p. 113
Some More Examples of CMOS Logic	p. 115
XOR or Nonequivalence Gate Using CMOS Logic	p. 116
XOR-XNOR or Equivalence Gate Using CMOS Logic	p. 116
And-Or-Invert and Or-And-Invert Gates	p. 117
Full Adder Circuits Using CMOS Logic	p. 118
Pseudo-nMOS Gates	p. 120
Why the Name Is Pseudo-nMOS?	p. 123
Ratioed Logic	p. 123
Operation of Pseudo-nMOS Inverter	p. 124
Pass-transistor Logic	p. 125
Complementary Pass Transistor Logic	p. 127
Signal Restoring Pass Transistor Logic Design	p. 128
Sizing of Transistor in CMOS Design Style	p. 129
Introduction to Logical Effort	p. 132
Definitions of Logical Effort	p. 132
Delay Estimation by Logical Effort	p. 135
Introduction to Transmission Gate	p. 136
Use of CMOS TG as Switch	p. 138
2:1 Multiplexer Using TG	p. 141
XOR Gate Using TG -141
XNOR Gate Using TG	p. 143
Transmission Gate Adders	p. 144
More Examples of TG Logic	p. 144
Tristate Buffer	p. 145
Transmission Gates and Tristates	p. 146
Implementation of Combinational Circuit Using DTMOS Logic for Ultra low Power Application	p. 149
ECLR Structure	p. 154
Power Consumption	p. 175
Propagation Delay	p. 175
References	p. 175
Advanced Energy-reduced Sequential Circuit Design	p. 177
Introduction to Sequential Circuit	p. 177
Basics of Regenerative Circuits	p. 177
Basic SR Flip-Hop/Latch	p. 181
NAND Gate-based Negative Logic SR Latch	p. 183
Clocked SR Latch	p. 183
Clocked JK Latch	p. 185
Toggle Switch	p. 186
Master-slave Flip-flop	p. 186
D Latch	p. 187
Positive and Negative Latch	p. 188
Multiplexer-based Latch	p. 188
Master-slave Edge-triggered Flip-flops	p. 190
Timing Parameters for Sequential Circuits	p. 192
Timing of Multiplexer-based Master-slave Flip- flop	p. 194
The Sizing Requirements for the Transmission Gates	p. 195
Clock Skews due to Nonideal Clock Signal	p. 196
Design and Analysis of the Flip-flops Using DTMOS Style	p. 197
SR Latch and Flip-flop	p. 197
JK Latch and JK Flip-flop	p. 201
D Flip-flop	p. 202
Adiabatic Flip-flop	p. 205
References	p. 207
Introduction to Memory Design	p. 208
Introduction	p. 208
Types of Semiconductor Memory	p. 208
Memory Organization	p. 210
Introduction to DRAM	p. 212
One-transistor DRAM Cell	p. 213
Write	p. 214
Hold	p. 214
Read	p. 215
Capacitor in DRAM	p. 217
Refresh Operation of DRAM	p. 219
DRAM Types	p. 220
FPM DRAMS	p. 220
Extended Data Out DRAMs	p. 221
Burst EDO DRAMs	p. 221
ARAM	p. 221
Cache DRAM	p. 221
Enhanced DRAM (EDRAM)	p. 221
Synchronous DRAM	p. 222
Double Data Read DRAMs	p. 222
Synchronous Graphic RAM	p. 222
Enhanced Synchronous DRAMs	p. 222
Video DRAMs	p. 223
Window DRAMs	p. 223
Pseudo-static RAMs	p. 223
Rambus DRAMs	p. 223
Multibank DRAM	p. 224
Ferroelectric DRAM	p. 224
SOI DRAM	p. 225
Operating Principle	p. 225
Design Considerations of SOI DRAM	p. 226
Introduction to SRAM	p. 226
SRAM Cell and Its Operation	p. 227
SRAM Cell Failures	p. 228
Performance Metrics of SRAM	p. 228
Static Noise Margin	p. 228
Reliability Issues of 6-T SRAM	p. 229
Read-only Memory	p. 230
EPROM	p. 233
Electrically Erasable Programmable Read-only Memory (E²PROM)	p. 234
Flash Memory	p. 236
Summary	p. 238
References	p. 239
Analog Low Power VLSI Circuit Design	p. 242
Analog Low Power Design: Problems with Transistor Mismatch	p. 242
Mixed-signal Design with Sub-100 nm Technology	p. 243
Challenges in MS Design in Sub-100 nm Space	p. 244
Lack of Convergence of Technology	p. 244
Digital Scaling	p. 245
Memory Scaling	p. 246
Analog Scaling	p. 247
Degraded SNR	p. 247
Degradation in Intrinsic Gain	p. 248
Device Leakage	p. 248
Mismatch due to Reduced Matching	p. 248
Availability of Models	p. 248
Passives	p. 248
RF Scaling	p. 249
Issues Related with Power Devices	p. 250
Basics of Switched-capacitor Circuits	p. 250
Resistor Emulation Using SC Network	p. 251
Integrator Using SC Circuits	p. 252
SC Integrator Sensitive to Parasitic	p. 255
Low Power Switched-capacitor Circuit	p. 256
Current Source/Sink	p. 258
Technique to Increase Output Resistance	p. 261
Low Power Current Mirror	p. 263
Use of Current Mirrors in IC	p. 263
Simple Current Mirror	p. 265
Wilson Current Mirror	p. 267
Cascode Current Mirror	p. 268
Low Voltage Current Mirror	p. 270
Fundamentals of Current/Voltage Reference	p. 273
Another Way to Obtain Simple Bootstrap Voltage Reference Circuit with Start-up Circuit	p. 279
Bandgap Voltage Reference	p. 282
Positive TC Voltage	p. 282
Negative TC Voltage	p. 283
An Introduction to Analog Design Automation	p. 284
Survey of Previous Analog Design Flow	p. 285
Analog and Mixed-signal Design Process	p. 288
Hierarchical Analog Design Methodology	p. 290
Current Status for the Main Tasks in Analog Design Automation	p. 292
Field-programmable Analog Arrays	p. 299
Summary	p. 301
References	p. 301
Index	p. 305
Table of Contents provided by Ingram. All Rights Reserved.

Search Results for "{{sharedState.searchQuery}}"

Low Power VLSI Design : Fundamentals

Hardcover

See All Available Copies

Low Power VLSI Design : Fundamentals

Hardcover

See All Available Copies

See All Available Copies

Overview

Categories

All Available Copies Find out more about shipping times from these sellers.

Table Of Contents

Overview

Product Details

Table Of Contents

All Available Copies

Availability

Featured

Condition

Format

Digital

Age

Grade

Categories

Print Size

Language

Search Results for "{{sharedState.searchQuery}}"

Low Power VLSI Design : Fundamentals

Hardcover

See All Available Copies

Low Power VLSI Design : Fundamentals

Hardcover

See All Available Copies

See All Available Copies

Overview

Categories

All Available Copies Find out more about shipping times from these sellers.

Table Of Contents

Overview

Overview

Product Details

Table Of Contents

All Available Copies